1. Field of the Invention
The present invention relates to a semiconductor memory device and method for reading and writing data therein, and more particularly, to a semiconductor memory device having a plurality of memory cells arranged in row and column directions, a word line corresponding to each memory cell row and a complementary bit line pair corresponding to each memory cell column, and method for reading and writing data therein.
2. Description of the Background Art
FIG. 8 is a block diagram showing an arrangement of a conventional static random access memory (hereinafter referred to as an SRAM). Referring to FIG. 8, this SRAM includes a plurality of memory cells 14a-14d (for simplicity four are shown in FIG. 8) arranged in row and column directions, word lines 13a and 13b corresponding to respective rows, and complementary bit line pairs 15a, 15b and 16a, 16b corresponding to respective columns.
As shown in FIGS. 9(a) and 9(b), memory cell 14a includes driver transistors 61a and 61b, access transistors 62a and 62b, load resistances 63a and 63b, and storage nodes 64a and 64b. Driver transistors 61a and 61b have their drains connected to storage nodes 64a and 64b, their gates connected to storage nodes 64b and 64a, and their sources connected to a ground line 51, respectively. Access transistors 62a and 62b have their sources connected to storage nodes 64a and 64b, their drains connected to bit lines 15a and 15b, and their gates connected to word line 13a, respectively. Load resistances 63a and 63b are each connected to a power supply line 50 at one end and connected to storage nodes 64a and 64b, respectively, at the other end. Other memory cells 14b-14d are similar to memory cell 14a.
This SRAM further includes a row address buffer 2 and a row address decoder 3 for selecting word line 13a or 13b in response to a row address-signal 1, a column address buffer 6 and a column address decoder 7 for selecting bit line pair 15a, 15b or 16a, 16b in response to a column address signal 5, and an address transition sensing circuit 4 for generating a bit line equalizing signal 9, a word line activation signal 10, a sense amplifier activation signal 11 and a latch signal 12 in response to transition of address signals 1 and 5.
This SRAM further includes bit line loads 17a-18b and equalizers 17c and 18c provided on one end of each of bit line pairs 15a, 15b and 16a, 16b, and column select gates 52 provided on the other end of each of bit line pairs 15a, 15b and 16a, 16b. Bit line loads 17a-18b are constituted by P-channel MOS transistors having their sources or drains connected to power supply line 50 or bit lines 15a-16b and their gates connected to ground line 51, respectively. Equalizers 17c and 18c are constituted by P-channel MOS transistors having their sources or drains connected to bit line pairs 15a, 15b and 16a, 16b and their gates receiving bit line equalizing signal 9 from address transition sensing circuit 4.
Column select gate 52 includes transfer gates 19a, 19b and inverter 19c corresponding to bit line pair 15a and 15b, as well as transfer gates 20a, 20b and inverter 20c corresponding to bit line pair 16a and 16b. Transfer gates 19a-20b respectively include a P-channel MOS transistor and an N-channel MOS transistor having their conductive electrodes connected to each other.
Transfer gates 19a and 19b are each connected to bit lines 15a and 15b at one conductive electrode and connected to IO lines 21a and 21b, respectively at the other conductive electrode, and have their gates on the side of the N-channel MOS transistors connected in common and further connected to column address decoder 7 through a column select line 8a. In addition, transfer gates 19a and 19b have their gates on the side of the N-channel MOS transistors connected to their gates on the side of the P-channel MOS transistors through inverter 19c. Transfer gates 20a, 20b and inverter 20c on the side of bit line pair 16a and 16b are similar to those on the side of bit line pair 15a and 15b.
This SRAM further includes a sense circuit 22, an output buffer 24 and an output latch 26. As shown in FIG. 10, sense circuit 22 includes a sense amplifier 70 and a tristate buffer 80. Sense amplifier 70 includes P-channel MOS transistors 71 and 72 constituting a current mirror circuit, N-channel MOS transistors 73 and 74 constituting a differential input circuit, and an N-channel MOS transistor 75 for activating or deactivating these circuits. P-channel MOS transistor 71, N-channel MOS transistors 73 and 75 are connected in series between power supply line 50 and ground line 51, and P-channel MOS transistor 72 and N-channel MOS transistor 74 are connected in series between power supply line 50 and a drain of N-channel MOS transistor 75. P-channel MOS transistors 71 and 72 have their gates connected in common and further connected to a drain of P-channel MOS transistor 71, and N-channel MOS transistors 73 and 74 have their gates connected to IO lines 21a and 21b, respectively, and N-channel MOS transistor 75 has its gate receiving sense amplifier activation signal 11 from address transition sensing circuit 4. A connection node between P-channel MOS transistor 72 and N-channel MOS transistor 74 forms an output node 76.
As shown in FIG. 11, tristate buffer 80 includes P-channel MOS transistors 81 and 82 as well as N-channel MOS transistors 83 and 84 connected in series between power supply line 50 and ground line 51. Transistors 84 and 81 have their gates receiving sense amplifier activation signal 11 and a complementary signal thereof 11, respectively, and transistors 82 and 83 have their gates connected to output node 76 of sense amplifier 70. A connection node 85 of transistors 82 and 83 forms an output node of this tristate buffer 80 and is connected to a read data bus 23.
As shown in FIG. 12, output latch 26 includes a transfer gate 91 and inverters 92-95, and transfer gate 91 includes an N-channel MOS transistor 91a and a P-channel MOS transistor 91b having their conductive electrodes connected to each other. Latch signal 12 from address transition sensing circuit 4 is input to a gate of N-channel MOS transistor 91a, and is also input to a gate of P-channel MOS transistor 91b through inverter 92. Transfer gate 91 has its one conductive electrode connected to read data bus 23, and the other conductive electrode connected to the one conductive electrode through inverters 93 and 95. Inverter 94 is connected between inverter 93 and the other conductive electrode of transfer gate 91.
FIG. 13 is a timing chart showing the operation of the SRAM shown in FIGS. 8-12. Description of read operation of this SRAM will now be given with reference to FIGS. 8-13.
Externally input row address signal 1 is applied to row address buffer 2 for outputting an amplified signal of row address signal 1 and an inverted amplified signal thereof, and an output of row address buffer 2 is applied to row address decoder 3 for decoding a row address signal which is output from row address buffer 2 and to address transition sensing circuit 4.
Meanwhile, externally input column address signal 5 is applied to column address buffer 6 for outputting an amplified signal of column address signal 5 and an inverted amplified signal thereof, and an output of column address buffer 6 is applied to column address decoder 7 for decoding a column address signal which is output from column address buffer 6, and to address transition sensing circuit 4. Column address decoder 7 selects column select line 8a or 8b corresponding to column address signal 5. For example, when column select line 8a is selected, column select line 8a rises to an "H" level as shown in FIG. 13(f), transfer gates 19a and 19b responsively become conductive, and bit line pair 15a and 15b as well as IO line pairs 21a and 21b become conductive.
Address transition sensing circuit 4 generates bit line equalizing signal 9, word line activation signal 10, sense amplifier activation signal 11 and latch signal 12, corresponding to transition of a row address and a column address. Timing of these signals 9-12 is such as shown in FIGS. 13(a)-(e). In response to transition of a row address and a column address, bit line equalizing signal 9 first falls to an "L" level, and then, word line activation signal 10 rises to an "H" level. Sense amplifier activation signal 11 rises to an "H" level in response to rise of word line activation signal 10, and latch signal 12 rises to an "H" level in response to rise of sense amplifier activation signal 11.
Bit line pairs 15a, 15b and 16a, 16b to which memory cells 14a, 14c and 14b and 14d are connected are precharged to a power supply potential by bit line loads 17a, 17b and 18a, 18b, respectively. When bit line equalizing signal 9 falls to an "L" level, equalizers 17c and 18c become conductive and potentials of bit line pairs 15a, 15b and 16a, 16b are equalized.
Row address decoder 3 selects word line 13a or 13b corresponding to row address signal 1 for a period determined by word line activation signal 10. For example, when word line 13a is selected, word line 13a rises to an "H" level as shown in FIG. 13(g), and memory cells 14a and 14b are responsively activated.
Operation of an activated memory cell, for example, 14a will now be described. Assume that a storage node 64a of memory cell 14a is at an "H" level and a storage node 64b thereof is at an "L" level. At this time, one driver transistor 61a of memory cell 14a is not conductive and the other driver transistor 61b is conductive. In addition, since word line 13a is at an "H" level and in a selected state, access transistors 62a and 62b of memory cell 14a are conductive. Accordingly, current flows through a path in the direction of bit line 15b, access transistor 62b, driver transistor 61b and ground line 51 (this current is hereinafter referred to as column current Ic). However, column current Ic does not flow through another path in the direction of bit line 15a, access transistor 62a, driver transistor 61a and ground line 51, since driver transistor 61a is not conductive.
In other words, when storage node 64a of activated memory cell 14a is at an "H" level and storage node 64b thereof is at an "L" level, column current Ic flows from bit line 15b into memory cell 14a and potential of bit line 15b decreases gradually. Similarly, when storage node 64a of activated memory cell 14a is at an "L" level and storage node 64b thereof is at an "H" level, column current Ic flows from bit line 15a into memory cell 14a and potential of bit line 15a decreases gradually. Accordingly, as shown in FIG. 13(h), potential of one of IO line pair 21a and 21b decreases gradually.
As shown in FIG. 10, IO line pair 21a and 21b are connected to gates of input transistors 73 and 74 of sense amplifier 70 of sense circuit 22, respectively. When sense amplifier activation signal 11 output from address transition sensing circuit 4 rises, N-channel MOS transistor 75 of sense amplifier 70 as well as P-channel MOS transistor 81 and N-channel MOS transistor 84 of tristate buffer 80 become conductive, and sense amplifier 70 and tristate buffer 80 are activated simultaneously.
In sense amplifier 70, since N-channel MOS transistor 73 and P-channel MOS transistor 71 are connected in series and P-channel MOS transistor 71 and P-channel MOS transistor 72 constitute a current mirror circuit, current of the same value flows through N-channel MOS transistor 73 and P-channel MOS transistor 72. If potential of IO line 21a is higher than that of IO line 21b, current flowing through N-channel MOS transistor 73 and P-channel MOS transistor 72 is larger than that flowing through N-channel MOS transistor 74, difference current therebetween flows into output node 76, and potential of output node 76 is pulled up. Contrary, if potential of IO line 21a is lower than that of IO line 21b, current flowing through N-channel MOS transistor 73 and P-channel MOS transistor 72 is smaller than that flowing through N-channel MOS transistor 74, difference current therebetween flows from output node 76, and potential of output node 76 is pulled down.
When potential of output node 76 of sense amplifier 70 is pulled up to an "H" level, P-channel MOS transistor 82 of tristate buffer 80 becomes non-conductive and N-channel MOS transistor 83 thereof becomes conductive, current flows from read data bus 23 through N-channel MOS transistors 83 and 84 into ground line 51, and potential of read data bus 23 is pulled down to an "L" level.
Contrary, when potential of output node 76 of sense amplifier 70 is pulled down to an "L" level, P-channel MOS transistor 82 of tristate buffer 80 becomes conductive and N-channel MOS transistor 83 thereof becomes non-conductive, current flows from power supply line 50 through P-channel MOS transistors 81 and 82 into read data bus 23, and potential of read data bus 23 is pulled up to an "H" level as shown in FIG. 13(i).
Output buffer 24 outputs read data signal 25, corresponding to data of read data bus 23. When read data bus 23 becomes attains an "H" level, read data signal 25 which is output from output buffer 24 also attains an "H" level as shown in FIG. 13(j).
When latch signal 12 output from address transition sensing circuit 4 rises, output latch 26 latches data of read data bus 23. In other words, when latch signal 12 rises to an "H" level in output latch 26 shown in FIG. 12, transfer gate 91 becomes conductive. For example, when read data bus 23 is at an "H" level, outputs of inverters 93, 94 and 95 are at an "L" level, an "H" level, and an "H" level, respectively. This state is maintained even if latch signal 10 falls to an "L" level and transfer gate 91 becomes non-conductive. After completion of latching, latch signal 12 becomes inactive. Then, sense amplifier activation signal 11 and word line activation signal 10 fall to an "L" level and read operation is completed.
However, in a conventional SRAM, operating current thereof has been large. In other words, since sense amplifier 70 and tristate buffer 80 are activated simultaneously by sense amplifier activation signal 11 as shown in FIGS. 10 and 11, transistors 81 and 84 of tristate buffer 80 are rendered conductive before potential of output node 76 of sense amplifier 70 is established to an "H" level or an "L" level, and current leaks from power supply line 50 through transistors 81-84 to ground line 51.
In addition, in the conventional SRAM, sense amplifier 70 continuously consumes direct current while sense amplifier activation signal 11 is at an "H" level and N-channel MOS transistor 75 of sense amplifier 70 is conductive.
In the conventional SRAM, word lines 13a and 13b are at an "H" level and column current Ic is consumed throughout data read operation.